IEEE CEDA PESU FDP 2026

The IEEE CEDA PESU FDP 2026 on "VLSI Design Tape Out Readiness" is a one of its kind vendor neutral platform faculty development programme where the academia is introduced, sensitised, and hands-on familiarised with various EDA tools, flows, techniques, and industry best practices towards tape-out readiness of VLSI IC design process, focussed on strengthening India's semiconductor circuits and system design ecosystem and preparing the next-generation workforce for the rapidly growing semiconductor industry.

Organised under the theme "Powering India's Semiconductor Future", the programme will bring together industry leaders, researchers, and professionals, to deliver curated programmes to the benefit of the academic faculty and senior research scholars in academia.

The event will feature keynote talks, expert technical sessions, panel discussions, hands-on sessions covering the complete semiconductor digital, analog and mixed-signal IC design, verification, test life cycle — from technology infrastructure like the PDKs and PCDs, Digital-on-Top (DOT) RTL-to-GDS flows, Analog-on-Top (AOT) Schematic-to-GDS custom design flows, architectural design, packaging, ESD, verification, DFT, electrical analysis and design sign-off aspects leading to not just tape out readiness but also a more comprehensive and holistic reliable, functional and testable chips that helps focus on the solutions for end applications more efficiently.

With India's semiconductor market and ecosystem projected to grow significantly in the coming years, the FDP aims to empower faculty with tools, techniques and knowhow to develop the next-generation talent pipeline.